Semiconductor device

ABSTRACT

A semiconductor integrated circuit device, such as a memory device or radiation detector, is disclosed, in which data storage cells are formed on a substrate. Each of the data storage cells includes a field effect transistor having a source, drain, and gate, and a body arranged between the source and drain for storing electrical charge generated in the body. The magnitude of the net electrical charge in the body can be adjusted by input signals applied to the transistor, and the adjustment of the net electrical charge by the input signals can be at least partially cancelled by applying electrical voltage signals between the gate and the drain and between the source and the drain.

RELATED APPLICATION

This application is a divisional application of application Ser. No.11/201,483 (still pending), filed Aug. 11, 2005, which is a divisionalapplication of application Ser. No. 10/450,238 (now U.S. Pat. No.6,969,662), filed Jun. 10, 2003, which is the National Stage ofInternational Application No. PCT/EP02/06495, filed Jun. 5, 2002, whichclaims priority to European Applications (i) EP 01 810 587, filed Jun.18, 2001, (ii) EP 02 405 247, filed Mar. 28, 2002, and (iii) EP 02 405315, filed Apr. 18, 2002.

BACKGROUND

The present invention relates to semiconductor devices, and relatesparticularly, but not exclusively, to DRAM memory devices using SOI(silicon on insulator) technology.

DRAM memories are known in which each memory cell consists of a singletransistor and a single capacitor, the binary 1's and 0's of data storedin the DRAM being represented by the capacitor of each cell being in acharged or discharged state. Charging and discharging of the capacitorsis controlled by switching of the corresponding transistor, which alsocontrols reading of the data stored in the cell. Such an arrangement isdisclosed in U.S. Pat. No. 3,387,286 and will be familiar to personsskilled in the art.

Semiconductor devices incorporating MOSFET (metal oxide semiconductorfield effect transistor) type devices are well known, and arrangementsemploying SOI (silicon on insulator) are becoming increasinglyavailable. SOI technology involves the provision of a silicon substratecarrying an insulating silicon dioxide layer coated with a layer ofsilicon in which the individual field effect transistors are formed byforming source and drain regions of doped silicon of one polarityseparated by a body of doped silicon of the opposite polarity.

SOI technology suffers the drawback that because the body region of eachindividual transistor is electrically insulated from the underlyingsilicon substrate, electrical charging of the body can occur undercertain conditions. This can have an effect on the electricalperformance of the transistors and is generally regarded as anundesirable effect. Extensive measures are generally taken to avoid theoccurrence of this effect, as described in more detail in a “Suppressionof parasitic bipolar action in ultra thin film fully depleted CMOS/simoxdevices by Ar-ion implantation into source/drain regions”, published byTerukazu Ohno et al. in IEEE Transactions on Electron Devices, Vol. 45,Number 5, May 1998.

A known DRAM device is also described in U.S. Pat. No. 4,298,962, inwhich the DRAM is formed from a plurality of cells, each of whichconsists of an IGFET (insulated gate field effect transistor) formeddirectly on a silicon substrate. This DRAM enables the injection ofcharge carriers from a semiconductor impurity region of oppositepolarity to the polarity of the source and drain regions and which islocated in the source or drain, or the injection of charge carriers fromthe silicon substrate.

This known device suffers from the drawback that it requires at leastfour terminal connections for its operation (connected to the drain,gate, source and impurity region of opposite polarity or to thesubstrate), which increases the complexity of the device. Furthermore,the memory function of each cell is ensured only while voltages arebeing applied to the transistor source and drain, which affects thereliability of the device, and writing, reading and refreshing of thestored information must be performed in so-called “punch through” mode,which results in heavy power consumption by the device.

An attempt to manufacture DRAM memories using SOI technology isdisclosed in U.S. Pat. No. 5,448,513. In that known device, each memorycell is formed from two transistors, one of which is used for writingdata to the memory cell, and one of which is used for reading datastored in the device. As a result of each cell consisting of twoseparate transistors, each cell requires four terminal connections forits operation, which increases the complexity of the device, as well asthe surface area necessary for each memory cell as a result of theprovision of two transistors.

Preferred embodiments of the present invention seek to overcome theabove disadvantages of the prior art.

SUMMARY OF THE INVENTION

According to an aspect of the present invention, there is provided asemiconductor device comprising

-   -   a substrate;

at least one data storage cell provided on one side of said substrate,wherein the or each said data storage cell comprises a respective fieldeffect transistor comprising (i) a source; (ii) a drain; (iii) a bodyarranged between said source and said drain and adapted to at leasttemporarily retain a net electrical charge generated in said body suchthat the magnitude of said net charge can be adjusted by input signalsapplied to said transistor; and (iv) at least one gate adjacent saidbody; and charge adjusting means for at least partially cancelling theadjustment of said net electrical charge by said input signals, byapplying first predetermined electrical voltage signals between at leastone corresponding said gate and the corresponding said drain and betweenthe corresponding said source and said drain. The present invention isbased upon the surprising discovery that the previously undesirablecharacteristic of excess electrical charge generated and retained in thebody of the transistor can be used to represent data. By providing asemiconductor device in which data is stored as an electrical charge inthe body of a field effect transistor, this provides the advantage thata much higher level of circuit integration is possible than in the priorart, since each data cell, for example when the semiconductor device isa DRAM memory, no longer requires a capacitor and can consist of asingle transistor. Furthermore, by generating said electrical charge inthe body of the field effect transistor (as opposed to in the substrateor in an impurity region provided in the source or drain), this providesthe further advantage that no specific connection need be made to thesubstrate or impurity region, thus reducing the number of terminalconnections necessary to operate the device.

In a preferred embodiment, said input signals comprise secondpredetermined electrical voltage signals applied between at least onecorresponding said gate and the corresponding said drain and between thecorresponding said source and said drain. The device may be a memorydevice.

The device may be a sensor and the charge stored in at least one saidbody in use represents a physical parameter. The input signals compriseelectromagnetic radiation.

The device may be an electromagnetic radiation sensor.

The device may further comprise a first insulating layer at leastpartially covering said substrate, wherein the or each said data storagecell is provided on a side of said first insulating layer remote fromsaid substrate.

The first insulating layer may comprise a layer of semiconductormaterial of opposite doping type to the body of the or each said datastorage cell. By providing a layer of material of opposite doping typeto the transistor body (e.g., a layer of n-type material in the case ofa p-type transistor body), this provides the advantage that by suitablebiasing of the insulating layer such that the body/insulating layerjunction is reverse biased, adjacent transistors can be electricallyisolated from each other without the necessity of usingsilicon-on-insulator (SOI) technology in which a layer of dielectricmaterial such as silicon oxide is formed on a silicon substrate. This inturn provides the advantage that devices according to the invention canbe manufactured using conventional manufacturing techniques.

The device may further comprise a respective second insulating layerprovided between at least one said body and/or each corresponding saidgate.

In a preferred embodiment, at least one said transistor includes aplurality of defects in the vicinity of the interface between at leastone corresponding said body and the corresponding said second insulatinglayer, for trapping charge carriers of opposite polarity to the chargecarriers stored in the body.

This provides the advantage of enabling the charge stored in the body ofthe transistor to be reduced by means of recombination of the storedcharge carriers with charge carriers of opposite polarity trapped in thevicinity of the interface.

The density of defects in the vicinity of said interface may be between10⁹ and 10¹² per cm².

The device may further comprise data reading means for causing anelectrical current to flow between a said source and a said drain of atleast one said data storage cell by applying third predeterminedelectrical voltage signals between at least one corresponding said gateand said drain and between said source and said drain.

The first insulating layer may comprise a plurality of insulatinglayers.

At least one said data storage cell may be adapted to store at least twodistinguishable levels of said electrical charge.

In a preferred embodiment, at least one said data storage cell isadapted to store at least three distinguishable levels of saidelectrical charge.

This provides the advantage that the more distinguishable charge levelsthere are which can be used to represent data in a data storage cell,the more bits of data can be stored in each cell. For example, in orderto represent n bits of data, 2^(n) distinguishable charge levels arerequired, as a result of which high density data storage devices can becreated.

At least one said transistor may have a drain/body capacitance greaterthan the corresponding source/body capacitance.

This provides the advantage of reducing the voltages which need to beapplied to the transistor to adjust the charge stored in the bodythereof, which in turn improves reliability of operation of the device.

The body of at least one said transistor may have a higher dopantdensity in the vicinity of said drain than in the vicinity of saidsource.

The area of the interface between the drain and body of at least onesaid transistor may be larger than the area of the interface between thesource and the body.

Common source and/or drain regions may be shared between adjacenttransistors of said device.

This provides the advantage of improving the extent to which the devicecan be miniaturised.

According to another aspect of the present invention, there is provideda method of storing data in a semiconductor device comprising asubstrate, and at least one data storage cell provided on one side ofsaid substrate, wherein the or each said data storage cell comprises arespective field effect transistor comprising (i) a source; (ii) adrain; (iii) a body arranged between said source and said drain andadapted to at least temporarily retain a net electrical charge generatedin said body such that the magnitude of said net charge can be adjustedby input signals applied to said transistor; and (iv) at least one gateadjacent said body; the method comprising the steps of: applying firstpredetermined electrical voltage signals between at least onecorresponding said gate and the corresponding said drain and between thecorresponding said source and said drain to at least partially cancelthe adjustment of said net charge by said input signals.

The method may further comprise the step of applying secondpredetermined electrical voltage signals between at least one said gateof a said data storage cell and the corresponding said drain and betweenthe corresponding said source and said drain.

The step of applying second predetermined said electrical signals mayadjust the charge retained in the corresponding said body by means ofthe tunnel effect.

This provides the advantage of enabling the charge adjustment to becarried out in a non-conducting state of the transistor in which theonly current is the removal of minority charge carriers from the body ofthe transistor. This in turn enables the charge adjustment operation toinvolve very low power consumption. This also provides the advantagethat a considerably higher charge can be stored in the body of thetransistor since, it is believed, the charge is stored throughoutsubstantially the entire body of the transistor, as opposed to just thatpart of the transistor in the vicinity of the first insulating layer. Asa result, several levels of charge can be stored, representing severalbits of data.

The charge may be adjusted by the application of a voltage signalbetween at least one said gate and the corresponding drain such that atthe interface between the corresponding body and the drain, the valenceand conduction bands of the body and drain are deformed to injectelectrons from the valence band to the conduction band by the tunneleffect, causing the formation of majority carriers in the body.

Said charge may be adjusted by means of tunnelling of electrons from thevalence band to at least one gate of a said field effect transistor.

The step of applying first predetermined said voltage signals maycomprise applying electrical voltage signals between at least one saidgate and the corresponding said drain such that at least some of thecharge carriers stored in the corresponding body recombine with chargecarriers of opposite polarity in said body.

This provides the advantage that the charge stored in the particulartransistor body can be adjusted without the transistor being switchedinto a conductive state, as a result of which the charge adjustment canbe carried out at very low power consumption. This feature is especiallyadvantageous in the case of a semiconductor device incorporating a largenumber of transistors, such as an optical detector in which individualpixels are provided by transistors.

The process, operating under the principle known as charge pumping, anddescribed in more detail in the article by G. Groeseneken et al., “Areliable approach to charge pumping measurements in MOS transistors”,IEEE Transactions on Electron Devices, Vol. 31, pp. 42 to 53, 1984,provides the advantage that it operates at very low current levels,which enables power consumption in devices operating according to theprocess to be minimised.

The method may further comprise the step of applying at least one saidvoltage signal comprising a first part which causes a conducting channelto be formed between the source and the drain, the channel containingcharge carriers of opposite polarity to the charge carriers stored insaid body, and a second part which inhibits formation of the channel,and causes at least some of said stored charge carriers to migratetowards the position previously occupied by said channel and recombinewith charge carriers of opposite polarity previously in said channel.

The method may further comprise the step of repeating the step ofapplying at least one said voltage signal in a single charge adjustmentoperation sufficiently rapidly to cause at least some of said chargecarriers stored in the body to recombine with charge carriers ofopposite polarity before said charge carriers of opposite polarity cancompletely migrate to said source or said drain.

BRIEF DESCRIPTION OF THE DRAWINGS

Preferred embodiments of the invention will now be described, by way ofexample only and not in any limitative sense, with reference to theaccompanying drawings, in which:

FIG. 1 is a schematic representation of a first embodiments of a MOSFETtype SOI transistor for use in a semiconductor device embodying thepresent invention;

FIG. 2 shows a sequence of electrical pulses to be applied to thetransistor of FIG. 1 to generate a positive charge in the body of thetransistor according to a first method;

FIG. 3 shows a sequence of electrical pulses to be applied to thetransistor of FIG. 1 to generate a negative charge in the body of thetransistor according to a first method;

FIG. 4 shows the variation in source-drain current of the transistor ofFIG. 1 as a function of gate voltage, with the body of the transistorbeing positively charged, uncharged and negatively charged;

FIG. 5 a is a schematic representation of an SOI MOSFET transistor of asecond embodiment for use in a semiconductor device embodying thepresent invention;

FIG. 5 b is a representation of the effect of the application of a gatevoltage to the transistor of FIG. 5 a on the valence and conductionbands of the transistor;

FIGS. 6 a to 6 c illustrate a first method embodying the presentinvention of eliminating a positive charge stored in the body of thetransistor of FIG. 1;

FIGS. 7 a to 7 d illustrate a second method embodying the presentinvention of eliminating a positive charge stored in the body of thetransistor of FIG. 1;

FIG. 8 is a schematic representation of a SOI MOSFET transistor of athird embodiment for use in a semiconductor device embodying the presentinvention;

FIG. 9 is a schematic representation of the gate, source and drain areasof a transistor of a fourth embodiment for use in a semiconductor deviceembodying the present invention;

FIGS. 10 and 11 show multiple charging levels of the transistor of FIG.1;

FIG. 12 shows multiple charging levels of the transistor of FIG. 1achieved by means of the methods of FIGS. 6 and 7;

FIG. 13 is a schematic representation of part of a DRAM memory deviceembodying the present invention and incorporating the transistor FIG. 1,5, 6, 7, 8 or 9;

FIG. 14 is a schematic representation of part of a DRAM memory device ofa further embodiment of the present invention and incorporating thetransistor FIG. 1, 5, 6, 7, 8 or 9;

FIG. 15 is a plan view of the part of the DRAM memory device of FIG. 14;

FIG. 16 is a cross-sectional view along the line A-A in FIG. 15;

FIG. 17 shows the development of integrated circuit processorperformance compared with DRAM performance; and

FIG. 18 is a schematic representation of an optical sensor embodying thepresent invention and incorporating the transistor of FIG. 1, 5, 6, 7, 8or 9.

DETAILED DESCRIPTION

Referring firstly to FIG. 1, an NMOS SOI (silicon on insulator) MOSFET(metal-oxide-silicon field effect transistor) comprises a silicon wafer10 coated with a layer 12 of silicon dioxide, the wafer 10 and layer 12constituting a substrate 13. A layer 14 formed on the substrate 13consists of an island 16 of silicon doped with impurities to form asource 18 on n-type material, a body 20 of p-type material and a drain22 of n-type material, together with a honeycomb insulating structure 24of silicon dioxide, the honeycomb structure being filled by a pluralityof islands 16. The source 18 and drain 22 extend through the entirethickness of the silicon layer 14. An insulating film 26 is formed overbody 20, and a gate 28 of doped semiconductor material is provided ondielectric film 26. The production process steps, chemical compositionsand doping conditions used in manufacturing the transistor of FIG. 1will be familiar to persons skilled in the art, and are also describedin further detail in “SOI: Materials to Systems” by A. J.Auberton-Hervé, IEDM 96. This publication also discloses thattransistors of this type have an electrical instability as a result ofthe fact that the body 20 is electrically floating, and can thereforeacquire an electrical charge, depending upon the sequence of voltagepulses applied to the transistor.

The transistor shown in FIG. 1 is of the type known to persons skilledin the art as “partially depleted” (PD), in which the depletion regions(i.e., those regions forming junctions between semiconductor types ofopposite polarity and which are depleted of free charge carriers) do notoccupy the entire thickness of the silicon layer 14.

Referring now to FIG. 2, in order to generate a positive charge in thebody of the NMOS transistor of FIG. 1, the gate voltage V_(g) and drainvoltage V_(d), as well as the source voltage, are initially zero. Attime t₀, the gate voltage is brought to −1.5V and at time t₀+Δt₀ (whereΔt₀ can be greater than, less than or equal to zero), the drain voltageV_(d) is brought to −2V, while the source voltage remains at zero. Byapplying a negative voltage pulse to the gate and a more negativevoltage pulse to the drain, a concentration of negative charge forms inthe body 20 in the vicinity of the gate 28, while a concentration ofpositive charge forms in the body in the vicinity of insulating layer12. At the same time, a conduction channel linking the source 18 anddrain 22 forms in the body 20, allowing conduction of electrons betweenthe source 18 and drain 22. This allows electrons to be attracted intothe channel from the source 18 and/or drain 22.

The application of a negative voltage to the drain 22 relative to thesource as shown in FIG. 2 generates electron-hole pairs by impactionisation in the vicinity of the source. The holes accumulated in thefloating body create a positive charge.

The drain voltage V_(d) then returns at time t₁ to zero, and the gatevoltage V_(g) returns to zero at t₁+Δt₁ to remove the conductive channelbetween the source 18 and drain 22, the time interval t₁-t₀ typicallybeing between a few nanoseconds and several tens of nanoseconds, whileΔt₁ is of the order of 1 nanosecond. It is also possible to create apositive charge in the body 20 by applying a positive drain voltagepulse, depending upon the voltages of the source, drain and gaterelative to each other. It has been found in practice that in order tocreate a positive charge in the body, the drain voltage must be switchedback to zero before the gate voltage.

Referring now to FIG. 3, a negative charge is generated in the body 20by increasing the gate voltage V_(g) to +1V at to while the source anddrain voltages are held at zero, then reducing the drain voltage V_(d)to −2V at time t₀+Δt₀ while the source voltage is held at zero. The gatevoltage V_(g) and drain voltage V_(d) are then subsequently brought tozero at times t₁ and t₁+Δt₁ respectively, where Δt₁ can be positive ornegative (or zero). The application of a positive voltage to the gate 28relative to the voltages applied to the source 18 and drain 22 againcauses the formation of a conductive channel between the source 18 anddrain 22, as was the case with the formation of an excess positivecharge as described above with reference to FIG. 2. The positive voltageapplied to the gate 28 also creates a concentration of negative chargein the body 20 in the vicinity of the gate 28, and a concentration ofpositive charge in that part of the body remote from the gate 28, i.e.,adjacent the insulating layer 12.

As a result of the application of the negative voltage to the drain 22,the body-drain junction is forward biased, as a result of which holesare conducted out of the body 20 to the drain 22. The effect of this isto create an excess of negative charge in the body 20. It should benoted that under these bias conditions the generation of holes by impactionisation is fairly weak. Alternatively, a positive voltage pulse canbe applied to the drain and the gate, as a result of which thebody-source junction is forward biased and the holes are removed fromthe body to the source. In a similar way, instead of generating anegative charge in the body 20, a positive charge stored in the body canbe removed.

Referring now to FIG. 4, the drain current I_(d) is dependent upon theapplied gate voltage V_(g), and the Figure shows this relationship for adrain voltage V_(d) of 0.3V, the curves 34, 36 and 38 representing thebody 20 having an excess of positive or negative charge, or zero excesscharge, respectively. It will therefore be appreciated that by theapplication of calibrated voltages to gate 28 and drain 22 and bymeasuring drain current I_(d), it is possible to determine whether body20 is positively or negatively charged, or whether it is uncharged. Thisphenomenon enables the transistor of FIG. 1 to be used as a data storagecell, different charging levels representing data “high” and “low”states, or some physical parameter to be measured, as will be describedin greater detail below.

Referring to FIG. 5 a, in which parts common to the embodiment of FIG. 1are denoted by like reference numerals but increased by 100, a furtherembodiment of an SOI transistor is shown in which the transistor iscaused to store a positive charge in its body 120 by means of the tunneleffect. The transistor of FIG. 5 a is manufactured by a succession ofphoto lithographic, doping and etching operations which will be familiarto persons skilled in the art. The transistor is made to 0.13 μmtechnology with a p-type dopant density of 10¹⁸ atoms per cm³ in thebody 120 and of 10²¹ n-type atoms per cm³ in the drain 122. Theinsulating layer 126 has a thickness of the order of 2 nm.

In order to operate the transistor of FIG. 5 a, the source is held at0V, the gate voltage V_(g) is −1.5V and the drain voltage V_(d) is +1 V.This causes the tunnel effect at the interface of the body 120 and drain122 as a result of the fact that the valence band B_(v) and conductionband B_(c), represented schematically in FIG. 5 b, are distorted.Folding of these bands can be achieved by an electric field of the orderof 1 MV/cm, which results in electrons being extracted by the drain 122,while the associated holes remain in the body 120. This physicalphenomenon is known as “GIDL” (Gate Induced Drain Leakage), described ingreater detail for example in the article by Chi Chang et al “CornerField Induced Drain Leakage in Thin Oxide MOSFETS”, IEDM TechnicalDigest, Page 714, 1987.

The charging operation of FIG. 5 a has the advantage over that describedwith reference to FIGS. 1 to 3 that the only current flowing during thecharging process is the extraction of electrons from the body 120 by thetunnel effect. As a result, charging occurs at very low powerconsumption. Furthermore, it has been found that the charge which can bestored in the body 120 is considerably higher (approximately twice aslarge) than that obtained by previous methods. It is believed that thisis as a result of the fact that a charge is stored throughout the entirevolume of the body 120, not just in that part of the body 120 adjacentto the insulating layer 112.

It will be appreciated by persons skilled in the art that the process ofFIG. 5 a, which was described with reference to NMOS transistors, canalso be applied to PMOS transistors, in which case the gate voltage ispositive and the drain voltage negative, and holes are extracted by thedrain while electrons are trapped.

Referring now to FIGS. 6 a to 6 c, in which parts common to theembodiment of FIG. 1 are denoted by like reference numerals butincreased by 200, a process is described for removing charge stored inthe body 220 of the transistor. It is important that the body 220 of thetransistor and the insulating film 226 be separated by an interface 230a few atomic layers thick which provides defects forming sites to whichelectrons can attach.

In order to remove the charge stored in the body 220, a cyclical signalshown in the upper part of FIG. 6 a is applied to the gate, the instantillustrated by FIG. 6 a being shown by an arrow in the insert.Initially, a potential of 0V is applied to the source 218 and drain 222,and then a potential of 0.8V is applied to gate 228. This has the effectof creating a conducting channel 232 at interface 230, and electrons areattracted into the channel 232 from the source 218 and/or drain 222. Thechannel 232 has a high density of electrons 234, as a result of thepositive voltage applied to gate 228, of which some are attached todefects at the interface 230.

When a voltage of −2.0V is then applied to gate 228, as indicated FIG. 6b, the channel 232 disappears, but the bound electrons 234 remain in theinterface 230. Moreover, the voltage applied to the gate 228 tends tocause holes 236 to migrate towards the interface 230 where theyrecombine with the bound electrons 234. As can be seen in FIG. 6 c, whena further cycle is applied beginning with the application of a voltageof 0.8V to gate 228, the channel 232 is again formed. However, comparedto the situation illustrated in FIG. 6 a, the number of holes 236 hasdecreased.

The interface 230 preferably has a defect density between 10⁹ and 10¹²per cm², this density and the number of oscillations necessary to removethe particles forming the stored charge representing an acceptablecompromise between device performance being limited by the number ofdefects and assisted by the number of trapped electrons. The pulseduration is typically about 10 ns, the rise and falling time being ofthe order of 1 ns. It should also be noted that in certain types oftransistors, it is also possible to form a channel between the source218 and the drain 222 in the vicinity of the insulating layer 212. Insuch a case, the conditions for recombination of charge carriers areslightly different, but the principle of operation is generally thesame.

FIG. 7 a shows a transistor identical in construction to that of FIGS. 6a to 6 c, but which enables the stored charge to be reduced more rapidlythan in the case of FIGS. 6 a to 6 c using recombination of charges atthe interface 230, but without having electrons bound to defects. FIG. 7a shows the state of the transistor before the charge reduction processis commenced, the body 220 having an excess of holes 236. By applying apositive voltage, for example 0.8V, to gate 228 as shown in FIG. 7 b,while keeping the source and drain at 0V, a channel 232 at the interface230 is created. The channel 232 contains an excess of electrons 234,depending on the positive voltage applied to the gate 228, the quantityof free electrons 234 significantly exceeding that of the holes 236present in the body 220 because of attraction of electrons into thechannel 232 from the source 218 and/or drain 222.

It can be shown that by rapidly reversing the polarity of the signalapplied to the gate 228, for example from 0.8V to −2.0V in a time of theorder of a picosecond, the electrons 234 located in the channel 232 donot have time t₀ migrate before the holes 236 contained in the body 220arrive in the space previously occupied by the channel 232, as shown inFIG. 7 c. The holes 236 and electrons 234 recombine in the interior ofthe body 220 without current flowing between the source and the drain,while the excess electrons 234 migrate towards the source 218 and thedrain 222. In this way, after a very short period of time, all of theholes 236 of the stored charge are recombined, as shown in FIG. 7 d.

In order to achieve the switching speeds necessary for the above processto be utilized in a semiconductor device, it is necessary to reduce theresistance and parasitic capacitances of the circuits and control linesas far as possible. In the case of memories, this can cause a limitationof the number of transistors per line and per column. However, thislimitation is significantly compensated by the significant increases inthe speed with which the stored charge is removed.

The charge removal process described with reference to FIGS. 6 and 7 canbe enhanced by providing an asymmetrical source/drain junction to givelarger junction capacitance on the drain side. In the arrangementdescribed with reference to FIGS. 1 to 3, it is observed that in orderto ensure fast writing of data states represented by the charge level(i.e., in a few nanoseconds), fairly high voltages need to be used, butthat these voltages need to be reduced by device optimization because ofreliability problems.

FIG. 8 shows a further embodiment of a transistor in which the voltagerequired to remove charge stored in the body of the transistor isreduced. During discharging of the charged body, pulses are applied tothe drain and to the gate of the transistor so that the body/source orbody/drain junction is biased in a forward direction. As a result, themajority carriers are removed from the charged floating body, providinga decrease in channel current when the transistor is switched to itsconductive state (see FIG. 4).

The potential of the floating body can be altered by adjusting thevoltages applied to the transistor contacts, or by altering thebody/source and/or body/drain and/or body/gate capacitances. Forexample, if the potential of the transistor drain is positive comparedto that of the source, the floating body potential can be made morepositive by increasing the capacitance between the drain and thefloating body. In the arrangement shown in FIG. 8, the MOSFET hasdifferent doping profiles for the drain and the source. In particular, aP+ doped region is formed in the vicinity of the drain, which leads toan increased capacitance between the drain and the floating body. Thisis manufactured by adding an implant on the drain side only, and bydiffusing this implant before forming the source and drain implantedregions. An alternative is to increase the capacitive coupling betweenthe drain and the floating body by using different geometries for thedrain and the source, as shown in FIG. 9.

The improved charging and discharging techniques described withreference to FIGS. 5 to 9 enable significantly greater currentdifferences between the uncharged and highest charged states of thetransistor to be achieved. For example, in the arrangement disclosedwith reference to FIGS. 1 to 3, the current difference between themaximum and minimum charge states is typically 5 to 2 μA/μm of devicewidth. For a 0.13 μm technology, where a typical transistor width of 0.2to 0.3 μm would be used, this means that a current difference of about 1to 6 μA is available. At least 1 μA of current is required to be able tosense the data represented by the charged state.

The charging and discharging arrangements disclosed with reference toFIGS. 5 to 9 provide a current difference as high as 110 μA/μm. Theavailability 110 μA/μm of signal for devices with 0.2 to 0.3 μm widthmeans that current differences of 22 to 33 μA per device can beachieved. As 1 μA is enough for detection, it can be seen that severallevels of charge can be stored in a single transistor body.

It is therefore possible to store multiple bits of data, for example, asshown in FIG. 10. FIG. 10 a shows a simple arrangement in which twolevels are available, and one bit of data can be stored. In FIGS. 10 band 10 c, multiple bits of data can be stored in states between themaximum and minimum charging levels. For example, to be able to storetwo bits of data, a total current window of 3 μA is required, while 7 μAis required to store three bits per device. With a total window of 33μA, five bits, corresponding to 32 levels, can be stored in the sametransistor. It will be appreciated that by storing a data wordconsisting of several data bits, as opposed to a single data bit, thestorage capacity of a semiconductor memory using this technique can besignificantly increased.

FIG. 11 shows the time dependence of a pulsed charging operation.Charging between different levels can be achieved by creating an initial“0” state, and then repeatedly writing “1” pulses, or by starting fromthe highest state, and repeatedly writing “0” pulses. One otherpossibility is to use different writing pulses to obtain differentstates, for example, by varying the writing pulse amplitude and durationto obtain a particular level.

A further possibility is shown in FIG. 12, which shows the levelsachievable using the charge pumping principle described with referenceto FIGS. 6 and 7. The amount of charge removed after each pulse causes acurrent decrease of Δls, and the various levels can be obtained bychanging the number of charge pumping pulses.

As pointed out above, the charge states of the body of the transistorcan be used to create a semiconductor memory device, data “high” statesbeing represented by a positive charge on body 20, and data “low” statesbeing represented by a negative or zero charge. The data stored in thetransistor can be read out from the memory device by comparing thesource-drain current of the transistor with that of an unchargedreference transistor.

A DRAM (dynamic random access memory) device operating according to thisprinciple is shown in FIG. 13. A DRAM device is formed from a matrix ofdata storage cells, each cell consisting of a field effect transistor ofthe type shown in FIG. 1, 5, 6, 7, 8 or 9, the sources of thetransistors of each row being connected together, and the gates anddrains of the transistors of each column being connected together, atransistor 32 ij corresponding to a transistor located on column I androw j, the transistor 32 ₂₂ being highlighted in FIG. 13. The gate 28,source 18 and drain 22 of transistor 32 ij are connected to conductivetracks 40 i, 42 i and 44 j, respectively. The conductive tracks 40, 42and 44 are connected to a control unit 46 and a reading unit 48, theconstruction and operation of which will be familiar to persons skilledin the art. The sources are earthed via the reading unit 48, or may beconnected to a given fixed potential.

The operation of the memory device shown in FIG. 13 will now bedescribed.

Initially, all gates (tracks 40) are at −2V, and all drains (tracks 44)and sources (tracks 42) are held at 0V. In order to write a data bit ofstate “1” to a transistor 32 ij, all tracks 40 of columns different fromi are still held at −2V, while track 40 i is brought to −1.5V. Duringthe time that the potential of track 40 i is −1.5V, all tracks 44 ofrows different from j are still held at 0V, while the potential of track44 j is brought to −2V. This process generates a positive charge in thebody of transistor 32 ij, as described above with reference to FIG. 2,the positive charge representing a single data bit of state “1”. Thepotential of track 44 j is then brought back to 0V, and the potential oftrack 40 i is subsequently brought back to −2V.

In order to write a data bit of state “zero” to the transistor 32 ij,from the condition in which all gates are initially held at −2V and allsources and drains are held at 0V, track 40 i is brought to a voltage of+1V, the other tracks 40 being held at −2V. During the time that thepotential of track 40 i is +1V, all tracks 44 of rows other than j areheld at 0V, while the potential of track 44 j is brought to −2V. Thisgenerates a net negative charge in the body of the transistor and thepotential of track 44 j is then brought back to 0V. The potential oftrack 40 i is then subsequently brought back to −2V.

In order to read the information out of the transistor 32 ij, thevoltage of tracks 40 of columns different from i is brought to 0V, whiletrack 40 i is held at 1V, and the voltage of tracks 44 of rows differentfrom j is brought to 0V, while track 44 j is held at +0.3V. As shown inFIG. 13, this then enables the current on track 44 j, which isrepresentative of the charge in the body of transistor 32 ij, to bedetermined. However, by applying a drain voltage of 0.3V, this alsoprovides the advantage that unlike conventional DRAM devices, thereading of data from transistor 32 ij does not discharge the transistor32 ij. In other words, because the step of reading data from the datastorage cell does not destroy the data stored in the cell, the data doesnot need to be refreshed (i.e., rewritten to the transistor 32 ij) asfrequently as in the prior art.

However, it will be appreciated by persons skilled in the art that theelectric charge stored in the body of transistor 32 ij decays with timeas a result of the electric charges migrating and recombining withcharges of opposite sign, the time dependence of which depends on anumber of factors, including the temperature of the device, or thepresence of radiation or particles such as photons striking thetransistor. A further application of this will be described in moredetail below.

In the memory unit described with reference to FIG. 13, each datastorage cell is formed by a transistor 32 disposed in an insulatinghoneycomb structure 24. The source and drain of neighbouring transistorsare located adjacent the drain and source of the two neighbouringtransistors in the same row, respectively. A DRAM device of a secondembodiment is shown in FIG. 14, in which parts common to the embodimentof FIG. 13 are denoted by like reference numerals. In the embodiment ofFIG. 14, for each row of transistors, other than those arranged at theends, each transistor shares its drain and source region with itsneighbours. This enables the number of tracks 42 and connections ontracks 44 to be reduced almost by a factor of 2.

A cross-sectional view of the DRAM device of FIGS. 14 and 15 is shown inFIG. 16, the view being taken along the line A-A in FIG. 15. The devicecomprises a substrate 13 including a silicon wafer 10 and insulatinglayer 12 as in FIG. 1, with sources 18, bodies 20 and drains 22 beingformed on the insulating layer 12. Dielectric films 26 are provided onbodies 20, and are extended upwards to the side of gates 28. The gatesare interconnected by tracks 40 and the sources 18 are interconnectedvia respective pillars 50 by tracks 42, the tracks 40, 42 extendingparallel to each other in a direction perpendicular to the plane of thepaper of FIG. 16. The drains 22 are interconnected via respectivepillars 52 by tracks 44 extending in a direction perpendicular to tracks40, 42, and of which only one is shown in FIG. 16.

As will be familiar to persons skilled in the art, in order toperiodically refresh the data contained in the cells of the memorydevice, alternate reading and writing operations can be carried out,with part of the charge detected during reading being supplemented inthe transistor in question. The refreshing frequency typically rangesfrom 1 ms to 1 second, a more detailed description of which is providedin ADRAM circuit design ISBN0-78036014-1.

As well as using charging of the body of a transistor as described aboveto construct a DRAM memory device, the charging process can be appliedto other types of memory, such as SRAM (static random access memory).One particular application is to cache SRAM applications. In modernmicroprocessors (MPU), the DRAM/MPU performance gap illustrated in FIG.17 has forced the MPU manufacturers to add some memory to the MPU. Thismemory is called cache memory. For example, the Intel 486 processor used8 Kbytes of cache memory. This memory is used to store information thatis needed frequently by the MPU. In modern Pentium processors, a secondlevel of cache memory, up to 256 Kbytes, has been added to keep upperformance. According to industry trends, next generation processors(the 10 Ghz Pentium processors for example) will require a third levelof cache memory having a density of 8 to 32 Mbytes of cache.

This memory has previously been provided by a 6 transistor SRAM cell(6T). The cell occupies typically an area of 100 to 150 F², where F isthe minimum feature size, which is quite large. Applying the chargestoring concept set out above, a 1T (1 transistor) cell can replace the6T transistor cell. Integrated in a logic technology, it can occupy a 10to 15 F² area, which is 10 times less. This is of significant importancesince integrating tens of Mbytes of 6T SRAM cells required die sizesmuch too large for practical fabrication.

As pointed out above, the charge stored on the body of a transistor canalso represent some physical parameter to be measured, for example theincidence of optical radiation. FIG. 18 is a schematic representation ofa CMOS image sensor embodying the present invention.

Image sensors have hitherto been made with a matrix of photosensitivedevices, each of which is provided with a MOS transistor acting as aswitch. To boost the information contained in each pixel, the pixelitself is also provided with an in-built amplifier. Such pixels arecalled active pixel sensors (APS) and typically include several devices:photo gate APS have typically 1 photosensitive capacitor and 4transistors. Photodiode APS have typically 1 photosensitive diode and 3or 4 transistors. In these APS devices the incoming light is incident onthe circuit (sometimes through a lens) and hits the sensitive element ofthe device. An integration cycle then allows charge generated by theincoming optical radiation to be accumulated and to generate anelectrical signal in a few ms or a few tens of ms. This signal is thenamplified and read. The matrix organization is similar to a memorymatrix organization, a typical pixel size being about 400 F², where F isthe technology minimum feature size.

In the arrangement shown in FIG. 18, it is possible to create a fullpixel with a single transistor that acts at the same time as lightsensitive element and as an amplifier. To achieve this, SOI transistorsare arranged in a matrix arrangement similar to that described for theDRAM applications above. The incoming light can come from the top orfrom the bottom (in this second case, an advantageous feature of SOItechnology being that the silicon substrate below the buried oxide canbe removed locally in the sensor matrix to provide an easy rear sideillumination option).

To operate the sensor, a reset operation is required, the resetoperation consisting of removing the majority carriers from the floatingbody (holes in the case of an NMOS transistor). For an NMOS device thismeans putting all devices in what is called a “0” state in the DRAMapplication. That this reset operation can be achieved by holeevacuation as described with reference to FIGS. 1 to 3, or morepreferably by the charge pumping technique described with reference toFIGS. 6 and 7. When the reset has been carried out (in typically 1 μs),the light then creates electron hole pairs in the body of the device.The minority carriers are removed through the junction and the majoritycarriers accumulate in the body, allowing the charge integration. Theinformation is read like in a DRAM memory, as explained above. The pixelarea achievable with such devices can be as small as 4F², or 100 timessmaller than in prior art devices. These imagers can be used in variousapplications, such as portable video recorders, digital photography, webcams, PC cameras, mobile telephones, fingerprint identification, and soon.

It will be appreciated by persons skilled in the art that the aboveembodiments have been described by way of example only and not in anylimitative sense, and that various alterations and modifications arepossible without departure from the scope of the invention as defined bythe appended claims. For example the process, described with referenceto NMOS transistors, can also be applied to PMOS transistors, in whichcase the stored charge is negative, i.e., formed by electrons, and thatthe free particles in the channel are holes. In that case, the channelis produced by the application of a negative potential to the gate.Also, in certain types of SOI transistors, the substrate can also act asa gate. In that case, the insulating layer performs the function of thedielectric film and the channel is formed at the interface of the bodyand the insulating layer. In addition, the invention can be applied toJFET (unction field effect transistor) technology as well as to theMOSFET technology described above. Furthermore, instead of providing alayer of insulating material on the silicon substrate, adjacenttransistors can be electrically isolated from each other by means of alayer of n-type silicon on the silicon substrate, and biasing the n-typesilicon layer such that the junction formed by the p-type transistorbody and the n-type silicon is reverse biased. In such cases, the bodyregion of each transistor should also extend below the correspondingsource and drain regions to separate the source and drain regions fromthe n-type silicon layer, and adjacent transistors are isolated fromeach other by means of a silicon dioxide layer extending downwards asfar as the n-type silicon layer.

1. An integrated circuit device comprising: a memory array, comprising:a plurality of dynamic random access memory cells arranged in a matrixhaving a plurality of rows and columns, each dynamic random accessmemory cell comprises a transistor comprising: a source region; a drainregion; a body region disposed between the source region and the drainregion, wherein the body region is electrically floating; and a gatespaced apart from the body region; and wherein each memory cell includesthree or more data states including: (1) a first data state whichcorresponds to a first charge in the body region of the transistor ofthe memory cell, (2) a second data state which corresponds to a secondcharge in the body region of the transistor of the memory cell, and (3)a third data state which corresponds to a third charge in the bodyregion of the transistor of the memory cell.
 2. The integrated circuitdevice of claim 1 further including read circuitry, coupled to thememory cells, to read the data state of the memory cell, wherein theread circuitry determines the data state of a given memory cell based onthe amount of charge in the body region of the transistor associatedwith the given memory cell.
 3. The integrated circuit device of claim 1further including read circuitry, coupled to the memory cells, to readthe data state of the memory cell, wherein the read circuitry determinesthe data state of a given memory cell based on the current output by thegiven memory cell in response to control signals applied to thetransistor associated with the given memory cell.
 4. The integratedcircuit device of claim 1 further including read circuitry, coupled tothe memory cells, to read the data state of the memory cell, wherein theread circuitry determines the data state of a given memory cell based onthe current output by the transistor associated with the given memorycell.
 5. The integrated circuit device of claim 1 further includingmeans for reading the data state of the memory cells.
 6. The integratedcircuit device of claim 1 further including: reading circuitry, coupledto the drain region of the transistor of each memory cell of a first rowof dynamic random access memory cells, to determine the data state ofeach memory cell of a first plurality of dynamic random access memorycells; control circuitry, coupled to gate of the transistor of eachmemory cell of the first plurality of dynamic random access memorycells, to provide control signals to each memory cell of the firstplurality of dynamic random access memory cells; and wherein, inresponse to a read control signal applied to the gate of the transistorof each memory cell of the first plurality of dynamic random accessmemory cells, the reading circuitry determines whether the memory cellis in a first data state, a second data state or a third data statebased on the charge stored in the body region of the transistor of thememory cell.
 7. An integrated circuit device comprising: a memory array,comprising: a plurality of memory cells arranged in matrix having aplurality of rows and columns, each memory cell consists essentially ofa transistor comprising: a source region; a drain region; a body regiondisposed between the source region and the drain region, wherein thebody region is electrically floating; and a gate spaced apart from thebody region; and wherein each memory cell includes three or more datastates including: (1) a first data state which corresponds to a firstcharge in the body region of the transistor of the memory cell, (2) asecond data state which corresponds to a second charge in the bodyregion of the transistor of the memory cell, and (3) a third data statewhich corresponds to a third charge in the body region of the transistorof the memory cell.
 8. The integrated circuit device of claim 7 furtherincluding read circuitry, coupled to the memory cells, to read the datastate of the memory cell, wherein the read circuitry determines the datastate of a given memory cell based on the amount of charge in the bodyregion of the transistor associated with the given memory cell.
 9. Theintegrated circuit device of claim 7 further including read circuitry,coupled to the memory cells, to read the data state of the memory cell,wherein the read circuitry determines the data state of a given memorycell based on the current output by the given memory cell in response tocontrol signals applied to the transistor associated with the givenmemory cell.
 10. The integrated circuit device of claim 7 furtherincluding read circuitry, coupled to the memory cells, to read the datastate of the memory cell, wherein the read circuitry determines the datastate of a given memory cell based on the current output by the givenmemory cell.
 11. The integrated circuit device of claim 7 furtherincluding means for reading the data state of the memory cells.
 12. Theintegrated circuit device of claim 7 further including: readingcircuitry, coupled to the drain region of the transistor of each memorycell of a first row of dynamic random access memory cells, to determinethe data state of each memory cell of a first plurality of dynamicrandom access memory cells; control circuitry, coupled to gate of thetransistor of each memory cell of the first plurality of dynamic randomaccess memory cells, to provide control signals to each memory cell ofthe first plurality of dynamic random access memory cells; and wherein,in response to a read control signal applied to the gate of thetransistor of each memory cell of the first plurality of dynamic randomaccess memory cells, the reading circuitry determines whether the memorycell is in a first data state, a second data state or a third data statebased on the charge stored in the body region of the transistor of thememory cell.
 13. An integrated circuit device comprising a memory array,disposed in or on a semiconductor region or layer which resides on orabove an insulating region or layer of a substrate, the memory arraycomprising: a plurality of memory cells disposed in or on thesemiconductor region or layer, wherein each memory cell comprises atransistor comprising: a source region having impurities to provide afirst conductivity type; a drain region having impurities to provide thefirst conductivity type, a body region disposed between the sourceregion, the drain region and the insulating region or layer of thesubstrate, wherein the body region is electrically floating and includesimpurities to provide a second conductivity type wherein the secondconductivity type is different from the first conductivity type; and agate spaced apart from the body region; and wherein each memory cellincludes three or more data states including: (1) a first data statewhich corresponds to a first charge in the body region of the transistorof the memory cell, (2) a second data state which corresponds to asecond charge in the body region of the transistor of the memory cell,and (3) a third data state which corresponds to a third charge in thebody region of the transistor of the memory cell wherein at least one ofthe data states is at least partially provided by removing majoritycarriers from the body region through the source region of thetransistor of the memory cell.
 14. The integrated circuit device ofclaim 13 further including read circuitry, coupled to the memory cells,to read the data state of the memory cell, wherein the read circuitrydetermines the data state of a given memory cell based on the amount ofcharge in the body region of the transistor associated with the givenmemory cell.
 15. The integrated circuit device of claim 13 furtherincluding read circuitry, coupled to the memory cells, to read the datastate of the memory cell, wherein the read circuitry determines the datastate of a given memory cell based on the current output by the givenmemory cell in response to control signals applied to the transistorassociated with the given memory cell.
 16. The integrated circuit deviceof claim 13 further including read circuitry, coupled to the memorycells, to read the data state of the memory cell, wherein the readcircuitry determines the data state of a given memory cell based on thecurrent output by the given memory cell.
 17. The integrated circuitdevice of claim 13 further including means for reading the data state ofthe memory cells.
 18. The integrated circuit device of claim 13 furtherincluding: reading circuitry, coupled to the drain region of thetransistor of each memory cell of a first row of dynamic random accessmemory cells, to determine the data state of each memory cell of a firstplurality of dynamic random access memory cells; control circuitry,coupled to gate of the transistor of each memory cell of the firstplurality of dynamic random access memory cells, to provide controlsignals to each memory cell of the first plurality of dynamic randomaccess memory cells; and wherein, in response to a read control signalapplied to the gate of the transistor of each memory cell of the firstplurality of dynamic random access memory cells, the reading circuitrydetermines whether the memory cell is in a first data state, a seconddata state or a third data state based on the charge stored in the bodyregion of the transistor of the memory cell.
 19. An integrated circuitdevice comprising memory array, disposed in or on a semiconductor regionor layer which resides on or above an insulating region or layer of asubstrate, the memory array comprising: a plurality of memory cells,arranged in a plurality of rows and columns and disposed in or on thesemiconductor region or layer, wherein each memory cell consistsessentially of a transistor comprising: a source region havingimpurities to provide a first conductivity type; a drain region havingimpurities to provide the first conductivity type, a body regiondisposed between the source region, the drain region and the insulatingregion or layer of the substrate, wherein the body region iselectrically floating and includes impurities to provide a secondconductivity type wherein the second conductivity type is different fromthe first conductivity type; and a gate spaced apart from the bodyregion; and wherein each memory cell includes three or more data statesincluding: (1) a first data state which corresponds to a first charge inthe body region of the transistor of the memory cell, (2) a second datastate which corresponds to a second charge in the body region of thetransistor of the memory cell, and (3) a third data state whichcorresponds to a third charge in the body region of the transistor ofthe memory cell.
 20. The integrated circuit device of claim 19 furtherincluding read circuitry, coupled to the memory cells, to read the datastate of the memory cell, wherein the read circuitry determines the datastate of a given memory cell based on the amount of charge in the bodyregion of the transistor of the given memory cell.
 21. The integratedcircuit device of claim 19 further including read circuitry, coupled tothe memory cells, to read the data state of the memory cell, wherein theread circuitry determines the data state of a given memory cell based onthe current output by the given memory cell in response to controlsignals applied to the transistor associated with the given memory cell.22. The integrated circuit device of claim 19 further including readcircuitry, coupled to the memory cells, to read the data state of thememory cell, wherein the read circuitry determines the data state of agiven memory cell based on the current output by the given memory cell.23. The integrated circuit device of claim 19 further including meansfor reading the data state of the memory cells.
 24. The integratedcircuit device of claim 19 wherein at least one of the data states issubstantially provided by removing majority carriers from the bodyregion through the source region of the transistor of the memory cell.25. The integrated circuit device of claim 19 further including: readingcircuitry, coupled to the drain region of the transistor of each memorycell of a first row of dynamic random access memory cells, to determinethe data state of each memory cell of a first plurality of dynamicrandom access memory cells; control circuitry, coupled to gate of thetransistor of each memory cell of the first plurality of dynamic randomaccess memory cells, to provide control signals to each memory cell ofthe first plurality of dynamic random access memory cells; and wherein,in response to a read control signal applied to the gate of thetransistor of each memory cell of the first plurality of dynamic randomaccess memory cells, the reading circuitry determines whether the memorycell is in a first data state, a second data state or a third data statebased on the charge stored in the body region of the transistor of thememory cell.